{"id":5439,"date":"2013-08-20T09:37:32","date_gmt":"2013-08-20T09:37:32","guid":{"rendered":"http:\/\/zukenblog.wpengine.com\/?p=5439"},"modified":"2024-02-13T11:44:44","modified_gmt":"2024-02-13T11:44:44","slug":"defining-and-routing-pcb-constraints-for-ddr3-memory-circuits-how-to-movies","status":"publish","type":"post","link":"https:\/\/www.zuken.com\/en\/blog\/defining-and-routing-pcb-constraints-for-ddr3-memory-circuits-how-to-movies\/","title":{"rendered":"Defining and Routing PCB Constraints for DDR3 Memory Circuits: How-to Movies"},"content":{"rendered":"

As Zuken technology partners, we are often asked about how best to set PCB constraints for double-data-rate (DDR) memory, and how to route to those constraints. This question arose recently when we were asked to create a common style of DDR3 design for training, and we tried mining the web for detailed information on PCB constraints. There had to be something out there, we thought.<\/p>\n

We were right; but unfortunately the detail had to be excavated from a vast and comprehensive pile of information about devices and controllers. It was hard to find a brief but clear description of what a PCB designer needs, and why, for a basic DDR3 circuit.<\/p>\n

PCB Design of a DDR3 Memory Circuit<\/b><\/h2>\n

Necessity being the mother of invention I worked with Kevan Keech, an expert PCB designer, \u00a0to create the most straightforward, realistic example we could think of \u2013 captured in three short movies.<\/p>\n

In the first movie I explain the circuit, routing topology and constraints.<\/p>\n

In the second movie, Kevan constrains the PCB design.<\/p>\n

In the final movie, Kevan routes the PCB design step-by-step and at the end we summarize the results.<\/p>\n

We use a single design example from start to finish \u2013 a controller connected to five 1-Gbitx8 SDRAM devices. Levelling is enabled so that the SDRAMs can be routed using fly-by topology, as defined in JEDEC standards\u00a0and elsewhere.<\/p>\n

After watching these movies, you will understand:<\/h2>\n
    \n
  • What key routing constraints you need for a memory circuit, such as that outlined in the movies<\/li>\n
  • How to adjust routing to balance impedance of lead-in and loaded sections as specified in JEDEC standards\u00a0and why you might need to do so<\/li>\n
  • How to place SDRAM components for optimum performance<\/li>\n
  • How to constrain the PCB design<\/li>\n
  • How to route accurately to DDR3 constraints<\/li>\n
  • How to ensure constraints have been met.<\/li>\n<\/ul>\n

    We hope you enjoy the movies and find them useful.<\/p>\n

    If you\u2019ve taken a look, why not leave a comment below!<\/p>\n

    <\/div>\n
    <\/div>\n
    <\/div>\n
    This blog post was co-written by John Berrie and Kevan Keech, based in the Zuken, Bristol, UK office.<\/span><\/div>\n","protected":false},"excerpt":{"rendered":"

    As Zuken technology partners, we are often asked about how best to set PCB constraints for double-data-rate (DDR) memory, and how to route to those constraints. This question arose recently when we were asked to create a common style of DDR3 design for training, and we tried mining the web for detailed information on PCB […]<\/p>\n","protected":false},"author":31,"featured_media":11146,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"om_disable_all_campaigns":false,"footnotes":"","_links_to":"","_links_to_target":""},"categories":[228],"tags":[264,15364,265,13464,277],"class_list":["post-5439","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-pcb-design","tag-constraint-management","tag-electronic","tag-high-speed","tag-how-to","tag-routing"],"acf":[],"yoast_head":"\nDefining and Routing PCB Constraints for DDR3 Memory Circuits - Zuken Blog<\/title>\n<meta name=\"description\" content=\"As Zuken technology partners, we are often asked about how best to set PCB constraints for double-data-rate (DDR) memory, and how to route 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