{"id":10710,"date":"2018-03-22T00:01:04","date_gmt":"2018-03-22T00:01:04","guid":{"rendered":"https:\/\/blog.zuken.com\/?p=9594"},"modified":"2025-02-20T15:52:01","modified_gmt":"2025-02-20T15:52:01","slug":"mastering-power-integrity","status":"publish","type":"post","link":"https:\/\/www.zuken.com\/en\/blog\/mastering-power-integrity\/","title":{"rendered":"Mastering Power Integrity: First Get Your Power Distribution System Right"},"content":{"rendered":"

I don\u2019t think I\u2019m generalizing when I say that designers working on complex high speed designs really don\u2019t want to expend a lot of time and effort dealing with power integrity problems. And they especially don\u2019t want to do it using tools that are detached from their design flow. In today\u2019s complex PCBs, we\u2019re talking advanced processors, complex FPGAs and superfast memories, which all share various voltage ranges.<\/p>\n

Even though power integrity strategies are now discussed on a daily basis, power distribution design is still a third order design aspect, done late in the design. It involves often a \u201cdesign-by-hope\u201d approach doing a copper pouring of the power-templates, and additionally sprinkling the board with decoupling capacitors. Such traditional methods of designing complex PCBs, and their power distribution systems (PDS) in particular, cost companies time and money in both the design and manufacturing stages.<\/p>\n

But it doesn\u2019t have to be this way<\/h3>\n

Here is an approach, using Zuken\u2019s embedded power integrity solution in CR-8000 Design Force<\/a>. The aim is to reduce unnecessary power layers in the board and to eliminate panic approaches, such as adding \u2018fear capacitors\u2019. The core concept behind this concurrent analysis solution involves designing the power distribution system (PDS) first to guarantee positive power integrity results as early as possible.<\/p>\n

\"Power
Figure 1: Power Integrity Analysis as an integral part of the layout process: 1.8V impedance distribution at 200 MHz<\/figcaption><\/figure>\n

It\u2019s all relative – EMC and the PDS<\/h3>\n

The overall performance and EMC behavior of electronic equipment is not only determined by the design of the circuitry and geometry of the layout, but also by the PDS. Parasitic noise voltages on the power\/ground system, caused by the fast switching of currents from integrated circuits (ICs), can lead to malfunctions and significant increases in electromagnetic emissions. High-speed components that utilize numerous complex high-pinout ICs, like FPGAs and CPUs operating on multiple voltage rails, add fuel to the fire.<\/p>\n

As these ICs become more of a commodity in electronics applications, the fight for the board real estate required to successfully transmit gigabit-speed signals gets more aggressive. So the traditional approach to address SI, PI and EMC in silos, disconnected from the board layout, is no longer appropriate.<\/p>\n

\"PCB-related
Figure 2: PCB related analysis disciplines<\/figcaption><\/figure>\n

Small changes \u2013 dramatic impact<\/h3>\n

The smallest change in component selection, placement, routing or power\/ground plane design can have a dramatic impact on the overall system performance. The PDS is critical. It is a the workhorse of the system providing operational voltage; supplying the current demands of all the active circuits; providing reference levels; implementing the current return paths for all the signal loops; and compensating for external noise. So the PDS needs to be designed rather than created by simply flooding layers with copper.<\/p>\n

Other issues that reinforce the need to design rather than simply create, include the need to provide charge over a wide frequency range, from low (e.g., system peripherals like disk drives) up to high frequencies, getting into the GHz range. The ongoing lowering of supply voltages and noise margins of today\u2019s ICs make the design of the PDS, and definition of its target impedances, a major design challenge.<\/p>\n

Designing the PDS right-first-time<\/h3>\n

Back when designers only had to deal with a few voltages, there was little need for extensive design to create a PDS. The overall board design process would start with the placement of ICs and routing of regular traces, followed by a definition of the area allocated for the PDS. The final stage in this process was simply to connect all the ICs to the PDS.<\/p>\n

The increased complexity and density of boards means that this simple approach is not as effective as it once was. The final stage is no longer just about connecting from A to B; purely because it is no longer physically possible. With today\u2019s complex boards, the approach has been to incorporate different layers for different voltages. But this has a negative knock-on impact on the cost of both design and manufacture. Alternatively, extra \u2018fear capacitors\u2019 can be placed on a board in the final stages of design to achieve power integrity. Again, this increases cost in both additional components and manufacturing. The recommended option that eliminates the requirement of extra layers or \u2018fear capacitors\u2019, involves designing the PDS first, and then placing the other components around it \u2013 ensuring power integrity from stage one.<\/p>\n

Effective PDS design<\/h3>\n

Fast analysis methodology including what-if capabilities for concurrent power integrity analysis is required. Full wave 3D solutions that can provide highly accurate results are unfortunately not applicable within the design process of most electronic systems, where time to market and time to volume are key. A systematic approach that provides design arbitration to achieve a balance between conflicting constraints is essential.<\/p>\n

\"Impedance
Figure 3: Impedance vs. frequency behavior of a complex CPU \u2013 achieved in one minute with a few mouse clicks<\/figcaption><\/figure>\n

The concept is simple: optimize analysis time invested to achieve reliable decision making results. In order to accomplish this, the new methodology requires that the available data is utilized throughout the design process, and that design consistency is maintained at all levels. EDA tools must manage the various design constraints with the ability to arbitrate between conflicting requirements.<\/p>\n

Concurrent design<\/h3>\n

A concurrent design solution, such as Zukens CR-8000<\/a>, integrates the power integrity methodology into the layout phase of the design process. It also ensures that a consistent set of design constraints, including power distribution and de-coupling requirements, is maintained throughout the design flow. Integrated EMC and power integrity verification is available within CR-8000 Design Force \u2013 where constraints conflict, this approach enables them to be resolved early in the design process. Features like adding virtual decoupling capacitors for conducting what-ifs, and parametric studies, and a dedicated solver to compute current distribution and DC voltages, complement the solution.<\/p>\n

\"Virtual
Figure 4: PDS-What-if – Impact of a ‘virtual’ decoupling capacitor<\/figcaption><\/figure>\n

Example \u2013 car navigation system<\/h3>\n

As an example, consider a car navigation system that includes a very small board with a fixed form factor. The unit needs to fit into the radio slot within the car. Boards like these feature high density IC technology such as FPGAs and CPUs, all with fast low power DDR3 (LPDDR3) memories and high-speed data links. The board also has to conform to a set power supply environment defined by the car manufacturer, and must comply very strict EMC limits. The challenge is then to fulfil all these demands to ensure power and signal integrity, and guarantee EMC. The PDS is designed first, and all the components are then placed and routed using the initial PDS design. Just as signal integrity requirements for high-speed systems require designers to organize the topology of connections to achieve clean signals, the architecture of power distribution systems must now be deliberately designed to prevent power integrity problems. But by using advanced design techniques (such as those in CR-8000) and using the concurrent analysis capabilities for SI and PI, costly extra board layers and increased component and manufacturing costs can be avoided.<\/p>\n

\"Embedded
Figure 5: Embedded PI analysis in Zuken\u2019s CR-8000 Design Force<\/figcaption><\/figure>\n

Find out more about Power Integrity in Zuken’s CR-8000<\/a><\/span><\/h3>\n","protected":false},"excerpt":{"rendered":"

\t\t\t\tI don\u2019t think I\u2019m generalizing when I say that designers working on complex high speed designs really don\u2019t want to expend a lot of time and effort dealing with power integrity problems. And they especially don\u2019t want to do it using tools that are detached from their design flow. In today\u2019s complex PCBs, we\u2019re talking advanced processors, complex FPGAs and superfast memories, which all share various voltage ranges. \t\t<\/p>\n","protected":false},"author":26,"featured_media":11294,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"om_disable_all_campaigns":false,"footnotes":"","_links_to":"","_links_to_target":""},"categories":[228],"tags":[11549,236,241],"class_list":["post-10710","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-pcb-design","tag-cr-8000","tag-power-integrity","tag-signal-integrity"],"acf":[],"yoast_head":"\nMastering Power Integrity: Sort Your Power Distribution System<\/title>\n<meta name=\"description\" content=\"Even though power integrity strategies are now discussed on a daily basis, power distribution design is still a third order design aspect, done late in the design\" \/>\n<meta name=\"robots\" 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