In the final installment of this blog series, you can learn how to use build-up layers and premium FPGAs to deal with the signal integrity challenges arising from high-speed signals in a 3D design capture world.<\/p>\n
![\"\"](\"\/\/blog.zuken.com\/wp-content\/uploads\/2017\/01\/BP-part-3-through-pin-component-300x175.png\")
Luckily, where signals need return vias, component vendors often do most of the work for you. Let\u2019s look at a PCI Express differential pair. \u00a0First, the standard connector, showing its pinout but not its body; I\u2019ll cover the connector body in a moment. The signal pin assignments are also standardized.<\/p>\n
This one is a through-pin component. The two sides of the differential pair (I\u2019ve marked them P and N), are close to ground pins. There\u2019s some differential coupling between the P and N pins and the ground pins create returns in the Z dimension, just like ground planes do for traces.<\/p>\n
The connector body works in a similar way. Here\u2019s a small area of the connector, mounted on its footprint. Inside the body, the differential pair has ground metal each side.<\/p>\n
![\"\"](\"\/\/blog.zuken.com\/wp-content\/uploads\/2017\/01\/BP-part-3-small-area-of-the-connector-300x259.png\")
So you can already route this pair from BGA to connector on, say, top and bottom layers, without adding any other vias. If you really need another layer change for a signal like this, then you have to decide on signal via-to-via and return via spacing.<\/p>\n
Let\u2019s look at the BGA itself. In this case, its balls are on a 1mm grid, fanned out to vias at even spacing. I\u2019ve added markers on the vias to show the differential pair (N and P) and surrounding ground vias. These signals are on a special high-speed transceiver bank on the FPGA. If you need another layer change, then one way to decide on spacing is just to copy this pattern.<\/p>\n
![\"\"](\"\/\/blog.zuken.com\/wp-content\/uploads\/2017\/01\/BP-part-3-BGA-300x241.png\")
You can\u2019t backdrill vias inside the area of a BGA like this, so the alternatives are blind vias or build-up layers. In any case, you often need build-up layers to achieve the high route density that BGAs like this demand. All that\u2019s required then is to restrict routing layers.<\/p>\n
Premium components like the FPGA mentioned here include features to help signals fly true. Some of the latest BGA footprints are so fine-pitched that many signals connect through via-in-pad to inner layers only with no room for tracks between pads.
\nNow that EDA environments work in three dimensions and with high levels of detail, it\u2019s much easier to visualize where signals are going and what will help or hinder them.<\/p>\n","protected":false},"excerpt":{"rendered":"
\t\t\t\tLuckily, where signals need return vias, component vendors often do most of the work for you. Let\u2019s look at a PCI Express differential pair. First, the standard connector, showing its pinout but not its body; I\u2019ll cover the connector body in a moment. The signal pin assignments are also standardized.\t\t<\/p>\n","protected":false},"author":31,"featured_media":11224,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"om_disable_all_campaigns":false,"footnotes":"","_links_to":"","_links_to_target":""},"categories":[228],"tags":[237,265,241],"class_list":["post-10641","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-pcb-design","tag-fpga","tag-high-speed","tag-signal-integrity"],"acf":[],"yoast_head":"\n